Due to advancements in information processing technology, complex integrated circuits (ICs) can be designed using various levels of abstraction. Using a hardware description language (HDL), circuits can be designed at the gate level, the register transfer level (RTL), and higher logical levels. When designing using an HDL, the designer describes the behavior of a system in terms of signals that are generated and propagated from one set of registers to another set of registers through combinatorial logic modules. HDLs provide a rich set of constructs to describe the functionality of each module. Modules may be combined and augmented to form even higher-level modules.
System-level integration relies on reuse of previously created designs that have been provided either from within an enterprise or from a commercial provider. Libraries of pre-developed blocks of logic have been developed that can be selected and included in a circuit design. Such library modules include, for example, adders, multipliers, filters, and other arithmetic and digital signal processing (DSP) functions from which system designs can be readily constructed. The library modules may further include memories and storage elements. The engineering community sometimes refers to these previously created designs as “design modules,” “cores,” “IP cores” (intellectual property cores), or “logic cores,” and such terms may be used interchangeably herein. The use of pre-developed logic cores permits faster design cycles by eliminating the redesign of circuits. Thus, using cores from a library may reduce design costs. Such logic cores may often be available for purchase by third parties who desire the functionality provided by the core, but do not have the time and/or resources necessary to design them.
Logic cores include a circuit design in the form of source code or a netlist that may be used in implementing the design in a programmable IC, such as a field programmable gate array (FPGA). Logic cores may be parameterizable. That is, the designer may specify values of parameters to tailor certain core functionality according to the designer's needs. The core may be integrated into a design by instantiating the code or netlist. The logic core is then placed and routed along with the rest of the design to provide the desired functionality.
Incorporation of a logic core into a larger design, however, may not be a simple task. For example, different logic cores included in a design may be configured to communicate using different bus protocols. In order to integrate a core, a designer often must create interface logic, sometimes referred to as “glue logic,” to connect the logic core to a standard bus used in the design. Integration can be a time consuming process. To ease the integration process, integrated software environments (ISEs) automate much of the integration process. These ISEs automatically generate wrapper code containing the required interconnect logic and allow the designer to configure some parameters of the core. This may be referred to as a core generation. High level modeling and design implementation tools, such as the System Generator for Digital Signal Processing (DSP) (SysGen), may be used to generate each core. SysGen, for example, provides a block diagram-based user interface for designing and debugging complex systems such as those involving highly parameterizable and reusable cores. The generated core is then placed and routed along with the rest of the design.
Both manual and automated integration methods result in an implementation unique to the selected parameters and generated interface. Although correct operation of a logic core may have been verified by the logic core provider, parameterization and interconnect logic generated by the designer or automated tool may change operation of the core. Thus, the function provided by the core must be verified after integration is completed. For this reason, a number of application areas, such as avionics, defense, etc., often require verification of the correct operation of the logic core as implemented in the circuit.
One verification method pre-verifies the processes implemented by automated integration tools. For example, an ISE can be tested to ensure that the integration process produces the same implementation for every instance of an imported logic core. The resulting implementation of the logic core can then be analyzed to pre-verify integration of a specific logic core using the automated tool. Once an integration process is verified for a logic core, correct integration of the core can be ensured. However, whenever the software tool is updated, verification of the software must be repeated for each core. This update process is complex and time consuming.
One or more embodiments of the present invention may address one or more of the above issues.